Layout Engineer

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.Requirements:Strong layout knowledge with a minimum of 3 to 4 years of experienceSkills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nmExperienced in digital (standard cell, memory, I/O) layoutExperienced in analog layout is also a plusJob Description:Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layoutSchedule time-line & layout floor-planningComplete quality layout and verification within planned schedule (without supervision for experienced engineer)Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library teamSkill Sets (IO):Extensive experience in full custom layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.Good experience in Floor-planning, hierarchy layout and chip integration.Understanding of Latch-up and ESD in CMOS process and implementation in layout design.Knowledge of Script Programming and SKILL Programming would be a plus.Review new design rules, compile documentation of layout methodology, layout flow and guidelines.Self-reliant, with ability to work independently as well as a team.Be trainer or leader to a team of junior engineers.Skill Set (Mem):Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.Good experience in Floor-planning, hierarchy layout and chip integration.Knowledge of Script Programming and SKILL Programming would be a plus.Able  to lead  or train a team of junior engineersGood knowledge on memory layout topology.Experience in memory compiler will be a plus.Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.Self-reliant, with ability to work independently as well as a team.Good leadership quality on project management.Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.