Summary Posted: Dec 19, 2022 Role Number: 200451398 Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products. Multifaceted, smart people and inspiring, innovative technologies are the norm here.
As a member of Mixed-Signal design team, you will build and support innovative design methodology and customize and automate CAD flows for sophisticated Mixed-Signal IP designs. The design flows are used by multiple different IPs of multiple projects at multiple sites. Proven understanding of Synthesis, P&R, Timing, Simulation CAD flows, EDA tools, UPF, algorithm, scripting (TCL/Perl/Python) and Makefiles is a requirement. You will collaborate with RTL, PD and timing design teams, CAD team, and EDA vendors. Key Qualifications Key Qualifications Typically requires extensive and relevant experience in Synthesis, PNR and timing flows development. Understand various aspects of partition level Synthesis, PNR, including floor-planning, timing/power optimization, CTS, routing the UPF Understanding and exposure to extraction and timing analysis flows Understand hierarchical Synthesis and PNR issues is a key (UPF, power-distribution, multi-voltage design) Deep Knowledge and experience of hard IP view set creation and deliverables Strong TCL/Perl/Python/Makefile scripting knowledge. Proven track record of managing, and regressing Synthesis, P&R and timing flows. Self-motivated, dedicated problem solver. Strong interpersonal/communication skills are a huge plus. Description Description As a member of the Mixed Signal Methodology team, you will be involved with all aspects of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to:
Provide innovative solutions to customize and improve quality and efficiency of mixed-signal design. Work with RTL and physical design teams to implement and customize design flows that are efficient for different IPs. Provide documentation, training and new-user-support. Responsible for diagnosis, resolution, regression of reported problems.
Generate block/chip level static timing constraints. Develop checks and flows for Hard IP deliveries and for sign-off. Develop and guide development of high performance low power clock networks.
Automate flows for timing ECOs, noise, and EM/IR violations.
Provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for accurate by construction designs. Assist in flow development for chip integration. Education & Experience Education & Experience BS degree in technical discipline with minimum 10 years of relevant experience.
Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. Additional Requirements Additional Requirements
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