GPU Physical Design Clocking Engineer

Summary Posted: Jan 9, 2023 Role Number: 200453771 Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU! You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions! Joining this group means crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for realizing the complete electrical analysis closure from early design planning to tapeout. Key Qualifications Key Qualifications Experience with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning, and hard IP integration. Deep experience planning, implementing, and analyzing high-speed clock distribution networks from the root to leaf. Exposure to different strategies for clock distribution including balanced trees, mesh, and forwarded clocks. Practical knowledge with hierarchical design approach, top-down design, budgeting, timing, and physical convergence will be an asset. Ability to comprehend Functional and Test clocking requirements in to design. Proven ability to use critical clock metrics revolving around latency, skew, and variation to prevent and solve sophisticated cross-hierarchy clocking issues. Showcase your experience on the design and integration of clocking IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain. Depth of expertise with large SoC designs (>20M gates) with frequencies in excess of 1GHz applying brand-new technologies. Experience planning and crafting test structures to evaluate clocking functionality and performance post Silicon. Background in engaging with Test teams pre/post Silicon to debug and analyze problems from a clocking perspective. Experience in technical project leadership and achieving results that have had impact on project completion and objectives. Track record of applying creative thinking to strategically solve problems that have impact for a project, group, or organization. Consistent record in solving complex PD and multi-functional problems, achieving results directly and/or leading a team of engineers to innovate and achieve extraordinary GPU designs. From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification is required. Further, experience with SPICE simulation/analysis and Physical Design Verification Flows is a plus. Description Description • Work closely with the RTL/FE teams to understand chip architecture and drive clocking aspects early in design cycle. • Drive best in class clocking construction and solutions for performance, power and Area (PPA). • Collaborate to drive clocking methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress. • Be focal point for all things clocking, drive the work among PnR engineers to set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. • Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution. • Communicate and drive the needs of PD and Clocking with multi-functional teams that will enable achieving the goals of the back-end design for the project. Education & Experience Education & Experience We are looking for candidates with a minimum of BS + 10 years of relevant experience. Additional Requirements Additional Requirements