CPU Cache RTL Architect

Summary Posted: Mar 24, 2023 Role Number: 200471185 Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! Apple’s Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products! We are looking for an experienced engineer that can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems. Key Qualifications Key Qualifications Minimum BS and 3+ years of relevant industry experience CPU RTL and architecture experience, or Doctorate degree with CPU design/architecture as research focus. Knowledge and experience with the following as it relates to CPU cache design: Coherence protocols and interconnects High performance (low latency, high bandwidth) design techniques Memory subsystem queuing, scheduling; starvation and deadlock avoidance SRAM design basics Multiple clock/power domains and power management strategies Prefetchers, replacement policies Debug capabilities DFT strategies Error detection and correction Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools. Experience in C or C++ programming and interpretive languages such as Perl or Python. Knowledge of logic design principles along with timing and power implications and understanding of low power microarchitecture techniques. Description Description As a cache subsystem architect, you will own or participate in the following: • Microarchitecture development and specification. From early high-level architectural exploration, through microarchitectural research and arriving at a detailed specification. • RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. • Performance exploration. Explore high performance strategies and work with the verification team to validate that the RTL design meets targeted performance. • Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power. Education & Experience Education & Experience Minimum BS and 3+ years of relevant industry experience Additional Requirements Additional Requirements Pay & Benefits Pay & Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $138,900 and $256,500, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.