Early Career Design Verification Engineer - Power Management (m/f/d)

Summary Posted: Aug 1, 2023 Role Number: 200493973 At Apple, we work every single day to craft products that enrich people’s lives! Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an ambitious and outstandingly talented Design Verification Engineer. As a member of our dynamic group, you will have the unique and exciting opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day! We are looking for a Design Verification Engineer who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. Key Qualifications Key Qualifications Deep knowledge of SystemVerilog and UVM Experience developing scalable and portable test-benches Experience with constrained random verification environments Experience defining coverage space, writing coverage model, analyzing results Experience with Assertion Based Verification Knowledge of Object Oriented Programming Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification) is a plus Experience with Python, Perl or TCL Excellent communication and interpersonal skills combined with the ability to collaborate Fluency in English is required Description Description In this role you will develop verification plans in coordination with design leads and architects. You'll be responsible for planning, building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Create functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a perfect verification flow. Education & Experience Education & Experience BSc or MSc in Electrical Engineering Additional Requirements Additional Requirements We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, colour, national origin, gender, sexual orientation, age, marital status, veteran status or disability status.