Summary Posted: Sep 11, 2023 Weekly Hours: 40 Role Number: 200502331 Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Key Qualifications Key Qualifications Master’s degree or foreign equivalent in Electrical Engineering, Computer Science, or a related field and 2 years of experience in the job offered or related occupation. 1 year of experience with each of the following skills is required: 1. RTL synthesis 2. Perl and TCL scripting 3. PrimeTime SI 4. UPF and CTS synthesis Description Description APPLE INC has the following available in West Lake Hills, Texas. Run Static Timing Analysis (STA) tools on design. Identify changes in the design that affect timing of the chip. Create Engineering Change Orders (ECOs) for fixing timing issues in the design. Collaborate with physical design team to highlight issues and best practices. Create and/or maintain scripts for runtime optimized and efficient analysis of the design to highlight timing flaws in design. Perform timing flow development to automate the STA flow to allow other teams to get results with a push button. Document and assist in creating guidelines and specs for timing of the product and integrate it at top level. Collaborate with design team to understand and debug timing constraints to ensure accurate analysis of the design. 40 hours/week. Education & Experience Education & Experience Additional Requirements Additional Requirements
View Original Job Posting