Early Career Design Verification Engineer - Power Management

Summary Posted: Oct 9, 2023 Role Number: 200509644 At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an ambitious and outstandingly talented Design Verification Engineer. As a member of our dynamic group, you will have the unique and great opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day! Apple’s PMU Hardware Tech team are responsible for delivering the power in a highly configurable and controlled way to the high end Apple SoCs, which power everything from Apple Watch, AirPods, and Apple TV to iPhone, iPad, Mac and Vision Pro. We are looking for an Early Career Digital Design Verification Engineer, with the talent, ambition and passion, to innovate the way we verify our next generation of power management silicon, to provide industry leading power efficiency, achieve customer expectations of device performance, battery efficiency, and welcome you to work among the industry’s best. The responsibilities include all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. Key Qualifications Key Qualifications Good understanding of System Verilog Basic understanding/experience of verification methodologies such as UVM, constrained random verification is desirable but not required Understanding of digital logic circuits Experience with digital logic simulation Experience with Python, Perl or TCL Understanding of Analog or mixed signal circuits is beneficial Ability to work well in a team and be productive under tight schedules Strong communications skills, self-motivated and well-organised, combined with ability to collaborate Strong analytical/problem solving skills Fluency in English is required Description Description - In this role you will develop verification plans in coordination with design leads and architects. You'll be responsible for planning, building and maintaining verification test bench components and environments. - Generate directed and constrained random tests. - Run simulations and debug design and environment issues. - Create functional coverage points, analyze coverage, and improve test environment to target coverage holes. - Craft automated verification flows for block and chip level verification. - Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs. - Work with other block and core level engineers to ensure an efficient verification flow. Education & Experience Education & Experience BSc/MSc/BEng/MEng/PhD in Electronic Engineering or equivalent field Additional Requirements Additional Requirements Some international travel may be required. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.