SOC Verification Engineer

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today. NVIDIA is an equal opportunity employer.Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.What you'll be doing:Work on cutting edge DFX functional technologies like In-System Testing and Test-Access Mechanism through Hi-Speed IO's.Build scalable and reusable verification methodologies and infrastructure to leverage them across different product lines.Writing test plan based on functional description documents, execute it using SV, UVM, NVIDIA custom tools/flows.Partner nwith cross-functional teams such as pads, BOOTROM, clocks, PCIE, Fuse, SOCD and DFT team for identifying design dependencies and verification deliverables expected from them.Work on verifying ATPG (LBIST, Stuckat, At-Speed) and MBIST patterns through In-System Testing at SOCV level.Work on both pre-silicon verification as well as post-silicon validation of the features.Own some modes of coverage that are typically applicable at full chip verification.Work with emulation/FPGA teams to bringup the use cases on emulation/FPGA platforms for enabling SW development.What we need to see:Btech/BE/BS or Mtech/ME/MS in EE/ECE or equivalent experience.3-6 years of experience.Experience with RTL verification.Debug proficiency related to full chip rtl test case failures and understanding of full chip topologies.Strong Coding skills in industry- standard scripting languages.Familiarity with BIST architecture and JTAG/IEEE1149.1/IEEE1500.UVM knowledge is a plus.Exposure to DFX circuits and methodology is desired.Outstanding written and oral communication skills with the curiosity to learn.