Senior ASIC Engineer - Emulation and FPGA

Are you passionate about FPGA prototyping? Are you interested in inventing new ideas to make FPGA prototypes more efficient? Can you work on a fast-paced environment needing coordination from many teams across geographies and resolving issues every day? If so, we are looking for hardworking engineers who will craft the FPGA prototype solutions of our next generation designs on standard FPGA prototyping platforms.What you’ll be doing:You are expected to understand the design and implementation, define the configurations, develop/modify the infrastructure, and verify the correctness of the design.Build the prototype infrastructure and standsim testbenches.Bring up the design on board and indulge in problem solving.Release the prototype to the customers and support them when they face problems.What we need to see:MS degree from EE/CS or related majors from a prestigious university.3+ years’ experience in ASIC design/verification or any emulation work.Exposure to ASIC design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB).Expertise in Verilog, System Verilog, C, C++.Good digital design concepts.Good debugging and problem-solving skills.Fluent English (both written and spoken) and excellent interpersonal skills.Self-motivated, proven ability to work independently as well as in a multi-disciplinary group environment.Ways to stand out from the crowd:Prior experience with C/C++/SystemC programming development is a plus.Scripting knowledge (Python/Perl/shell/Tcl) is desired.Experience in system/SOC/Full chip level verification desirablePrior experience with hardware emulation or prototyping (Synopsys HAPS, Zebu, Cadence Protium, Palladium, Mentor Veloce) of a high-performance processor or SOC is a plus.Hands on experience with lab debug equipment, such as oscilloscopes and logic analyzers.We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.