Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Broadcom’s Physical Layer Products (PLP) group is seeking an experienced engineer for digital logic implementation for SerDes IP blocks running at rates up to 64 Gb/s for PCIE, Ethernet, JESD,CPRI and SAS/SATA standards.Interface with RTL designers, analog designers, and customers to develop synthesis constraints for digital logic running at speeds over 4 GHz. Insert DFT logic to digital logic to meet challenging customers coverage metrics. Work with layout engineers to achieve timing closure on sub blocks as well as top of SerDes macro. Support customers, both internal and external, in the integration of SerDes IP.Tasks and required tools include:Synthesis of RTL:Tools used: Synopsys Design Compiler NXT and Fusion CompilerDFT insertion/verification:Tool: Synopsys DFT Compiler & Siemens TessentConstraint generation:Generate Multiple Constraint files for Multi-Frequency Functional and At-Speed TDF Scan_capture and 1/4 rate mode Scan_capture. Constraint file creation for Scan_shift and membist modes. Translate Top level and analog core (Acore) Lib models into proper I/O constraint requirements for all modes described above.Formal verification:Tool: Synopsys: FormalityRun formal comparison of RTL to netlist for verification of proper functionality at all stages of development.Interface with Layout Engineering:Provide netlist, constraint files, layout guidance file, and cts_directive file (which will help Layout Engineer insert proper balanced or fast/slow insertion delays on clocks as required for the design to meet timing requirements).Static Timing Analysis:Tool: PrimetimeEvaluate post layout netlist and parasitics against design timing requirements and layout DRC checks.Provide layout modifications to resolve all timing/DRC issues.Provide static/dynamic power recovery modifications to design without impacting timing/DRC issues.Post-Layout DFT verification:Tool: Synopsys DFT Compiler and Siemens TessentExtract Scan_chains using tool. Follow proprietary design flow to generate customer required dft top level support files: ctl, tcd_bscan, tcd_scan, no_fault flop reports.Customer Integration Support:Interface with all customers using IP and help with the integration into their SOC.Includes the generation of Clocking Diagrams which help explain the complex clocking structure of the IP for functional and DFT modes.Experience : Bachelors and 12+ years of related experience; at this level a post-graduate degree is typically expected or Masters degree and 10+ years of related experience or PhD and 7+ years of related experienceAdditional Job Description:Compensation and BenefitsThe annual base salary range for this position is $126,000 - $210,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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