Senior SOC IP Methodology Engineer

NVIDIA is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP solutions. We are looking for special individuals with passion and desire to deliver innovative products. Together, we will build the next generation of life changing SoC’s. If you are a motivated individual that understands how SoC systems are architected and built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be.What you will be doing: Responsible for developing and optimizing semicustom RTL to GDS methodologies, work with internal and external stakeholders and IP Vendors on SOC/IP requirements and drive technology alignments across them.Hands-on domain expert, able to traverse from RTL to final design closure (timing and layout) involving latest EDA technologies and capabilities.Work with customers on SOC/IP development processes, IP quality and handoff requirements for QA, smooth integration, and high-quality analysis flows.Drive, review, and cultivate development processes to assure top quality deliverables to and from IP customers and SOC engineers.Driving technical design reviews, assuring that defined processes are followed, identifying, and mitigating risks, and continuing to improve development processes with state-of-the-art tools and procedures.Responsible for deliverables/handoffs to and from Customers, methodology solutions and schedule plans.Drive early PPA on customer IP and drive what-if experiments to help drive KPI targets, analyze and solve critical issuesInternal and external stakeholders to carry out floorplan experiments to drive area estimates and evaluate solution tradeoffs.What we need to see: Experience working in a SOC development and customer focused environment with excellent communication skills.Require experience in handling complex IP ecosystem involving both internal and external partners. Exposure to IP-XACT or similar infrastructure is a plus.Proven hands-on experience with RTL-to-GDSII tool flows. physical design and analysis tools from EDA vendors such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT-SI, Tempus, Redhawk) etc.Demonstrated ability to work with ambiguous requirements and drive them to production quality KPI targets.Understanding of full flow (including DFT, BIST) to integrate customer and third-party IP and drive program alignment.Proven abilities to optimize methodology and flows for high productivity, design optimization and incorporate innovation.Background and knowledge in Synthesis, CTS, Power Optimization, Placement and Route methods and timing convergence for high performance designs like CPU, GPU and machine learning IPs.Abilities to work across teams and with customers to leverage reference flows and provide feedback on future tool/methodology improvements and needs.Scripting skills involving Python, Perl and Tcl, excellent soft skills.RTL2GDS experience with high performance ARM cores, Serdes, DDR, GPU, machine learning experience would be a plus.Masters (or equivalent experience) with 10+ (or BS with 12+) years of experience within these skill areas.The base salary range is $180,000 - $287,500. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.You will also be eligible for equity and benefits.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.