R&D Engineer IC Design

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:The prospective candidate will be an expert in SCAN and Memory BIST methodologies spanning from implementation to post-silicon bring-up and debug. He/She will be responsible for block-level and chip-level implementation of SCAN and MBIST including but not limited to pre-layout gate-level verification, timing analysis, post-layout gate-level verification with and without timing as well as pattern generation for post-silicon bring-up. He/She must be strong in DFT fundamentals and will have in-depth knowledge of compression-based SCAN and MBIST implementation tools like Mentor fastscan, Tessent MBIST etc., He will have good fundamentals of timing-analysis using industry-standard tools like PTSI etc. and needs to interact with physical design team to clean-up constraints and achieve good quality timing-closure. He/She must be highly self-motivated with very little or no need of supervision. He/She must be a good team-player and willing to mentor and teach junior team membersBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.