DFT Engineer

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Broadcom's ASIC Product Division is seeking candidates for a DFT Lead position at our San Jose, California development center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.The candidate would be required to work on various phases of SoC DFT related activities for Broadcom  APD (ASIC Products Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.Responsibilities:Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASICImplementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integrationWorking closely with STA and DI Engineers design closure for testGenerating, Verifying & Debugging Test vectors before tape release.Validating & Debugging Test vectors on ATE during the silicon bring up phaseAssisting with silicon failure analysis, diagnostics & yield improvement effortsInterfacing with the customer, physical design and test engineering/manufacturing teams located globallyWorking closely with I/P DFT engineers & other stakeholdersDebugging customer returned parts on the ATEInnovating newer DFT solutions to solve testability problems in 7nm & beyondAutomating DFT & Test Vector Generation flows Skills/Experience:Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)Well-versed in ATPG vector generation, simulation, debugExperience in Verilog coding, testbench generation & simulationMemory BIST insertion and verification experience The ability to work in a multi-disciplined, cross-department environmentSolid knowledge in analog and digital circuit design, and device physics fundamentalsGood understanding of Si processing, logical and physical synthesis, and transistor reliability principlesExcellent problem solving, debug , root cause analysis and communication skillsExperience working on ATE is a plusEducation & Experience:Bachelors Degree in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering, 6+ years of relevant industry experience.Additional Job Description:Compensation and BenefitsThe annual base salary range for this position is $106,800 - $178,000.This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.