ASIC Design Verification Engineer

Company: Broadcom
Company: Broadcom
Location: USA-CA Irvine Alton Parkway Bldg 2
Commitment: Full time
Posted on: 2023-05-08 05:07
Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Would you like to become part of a growing team developing silicon products for datacenters and other cloud operators?  Come join the team creating technology that fuels next generation AI and cloud megadatacenters! These programs are at the leading edge in a series of high throughput Ethernet controllers that deliver unprecedented performance at critically important power efficiency.We are looking for highly skilled and efficient Design Verification engineers that want to verify new designs that can evolve rapidly over the next several generations in a very dynamic market using industry proven constrained random methodologies with System Verilog and UVM.  You can become a member of an extremely skilled and efficient group of engineers. Broadcom intends to provide a complete interconnect solution with Controller and associated switch products – with performance enhancements when using an all Broadcom solution. This architecture will scale from traditional x86 servers to an emerging microserver segment, and all the way to high core count ARM-based SoCs.This is a rare opportunity to be part of an emerging product line, with market dominating products for a new line of devices. You will work with our worldwide design and architecture team, along with members of our Switch Team partners, to develop world class devices. All aspects of Design Verification, will be involved, along with opportunities for technical leadership.Requirements include: Skills:  Self motivated personality with a strong presence to do things right. Need to have strong sense of teamwork and ability to work well with other.  Constrained random verification methodologies with experience driving completion via coverage closure. Need to have skills with SV and UVM, well versed in OOPTools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...) Education and Experience:  BS in Electrical Engineering and 8+ years of related experience or an MS in Electrical Engineering and 6+ years of related experience.Additional Job Description:Compensation and BenefitsThe annual base salary range for this position is $91,200 - $152,000.This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.  Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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