Search JobsJob DescriptionWe are CPU & Server Platform R&D team under Cloud Infrastructure Business Group (CIBG) in VMware. In this role you will be part of Hardware team creating next generation HW accelerators that significantly influence Data center virtualization. You would join a cross-discipline team of highly capable and motivated engineers, designers, and validators. You will have the opportunity to transform your ideas into World-changing technologies & Products for Datacenter growth. Work with Research Groups, Platform Engineering teams at all layers of Hardware & Software - from FPGA BS to Firmware to OS (ESXi) to Hypervisors. You will have the opportunity to influence external FPGA, Silicon & platform vendors and VMW partners.What you will be responsible forBuild and maintain a UVM verification environment for FPGA development, at both the block, and system levels – that includes creating behavioral models to drive and check designs consisting of RTL, and third-party IP blocks.Assist in architecture, design implementation and verification/validation of custom design targeted for FPGA (or ASIC)Develop test plans, implement tests and analyze the coverageBuild and maintain the simulation environment to efficiently run, collect results, in a timely and clear fashionLead collaborative technical discussions to drive resolution on issues with internal teams and external HW partnersDevelop knowledge of system architecture, technical debug & validation strategyBe able to work in a high demand, fast paced environment with lots of real-time problem solving and critical thinkingRequirementsBS in Electrical Engineering or equivalent.Extensive experience in Micro-architecture and logic design of Compute and Storage SOC’sExperience in IP/SoC front-end RTL designGood understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysisGood understanding of common on-chip bus protocols such as PCIe, AXI8+ years of experience in ASIC/FPGA verification with UVM environments.Knowledge of logic design principles along with timing and power implicationsFluency in system Verilog/UVM.Experience in Verilog simulators and coverage tools.Have developed random verification tests utilizing constrained-random, functional coverage, and assertion.Familiar with standards such as networking protocol, PCIE, and memory interfaces is a plus.Familiar with shell and scripting languages (Perl, Python, …)Familiarity with SGE and similar is a plusC/C++ knowledgeA great team player with Good attitude, aptitude with ‘can do’ driveA great team player with Good attitude, aptitude with ‘can do’ driveFor US based candidates, the annual pay range (OTE for commissioned roles; Salary for other roles) for this position is: $101,000 - $230,000. The actual offer will be based on the role, location, and individual candidate experience. Bonus, commission, and/or equity may be eligible for this position. VMware offers comprehensive benefits including, but not limited to: medical, dental, and vision plans, company paid holidays, paid sick leave, and vacation time. Additional benefits for this position can be found at https://benefits.vmware.com/. Your talent advisor can share more about the specific salary range for your preferred location during the hiring process.This job may require the candidate to travel and/or work from a facility that requires full vaccination prior to entry.VMware is an Equal Opportunity Employer and Prohibits Discrimination and Harassment of Any Kind: VMware is committed to the principle of equal employment opportunity for all employees and to providing employees with a work environment free of discrimination and harassment. All employment decisions at VMware are based on business needs, job requirements and individual qualifications, without regard to race, color, religion or belief, national, social or ethnic origin, sex (including pregnancy), age, physical, mental or sensory disability, HIV Status, sexual orientation, gender identity and/or expression, marital, civil union or domestic partnership status, past or present military service, family medical history or genetic information, family or parental status, or any other status protected by the laws or regulations in the locations where we operate. VMware will not tolerate discrimination or harassment based on any of these characteristics. VMware encourages applicants of all ages. VMware will provide reasonable accommodation to employees who have protected disabilities consistent with local law. Search Jobs
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