Senior Engineer - Design

About InfineraInfinera is one of the world's leading providers of carrier-class optical networking products and services worldwide. Our solutions carry data over subsea optical cables, between cities and data centres. Infinera is building the next generation of pluggable optical modules and compact open modular optical systems.Infinera India Pvt. Ltd, Bangalore, is the largest Engineering group within Infinera with a team of 400+ people and is a critical execution team since the past 15 years.Infinera India ASIC team provides ASIC and FPGA solutions for all client facing interfaces in Infinera's systems. A dedicated team of 70 ASIC engineers gets to own and work on the Architecture, Design, Verification of Next Generation client interface solutions.As a company, Infinera has a culture and history of challenging conventional engineering thinking.The ASIC team takes pride in its engineering acumen, its teamwork, and the difference it makes to the quality and timeliness of our ASIC solutions.We are looking to add passionate, highly motivated, and talented Engineers to our mix of seasoned Engineers and fresh college graduates.What we offer:Opportunities to create solutions to challenging technical problems in area of ASICsA view of system level thinking and processes – you get to see the bigger picture, while developing your nicheA space for continuous learning through open communication and white-board discussionsOpportunity to master IEEE and ITU standardsA technically stimulating environment while providing a good work life balanceWork as part of a team comprising of end-to-end expertise, architects, protocol experts, implementation experts in design and verification, emulation, platform experts who develop SW and FWSenior Engineer - DesignRole:In this role you are expected to work with architects to understand the requirements, document them and implement the functional block or an IP.What you will be doing:Work closely with Architects to understand the requirements, document them, and implement the functional block or an IPCapture the design intent, uArch, RTL coding, API coding, lint, constraints development, CDC, and synthesisDebug the designs and work with verification team members to get a functionally clean blockIntegrate blocks and create physical design blocks for place and routeWork with Physical Design team to ensure that the design meets area, timing, power requirementsTest their design block in the lab and work with lab validation team membersWhat we seek:Ability to abstract complex functionsAbility to do the uArch using block diagrams, waveforms and mathematical and logical models/equationsGood understanding of use of FIFOs, state machinesExposure to RTL coding using Verilog/system VerilogGood logic design skills with ability to understand timing, area and power reportsExperience in timing constraints development, running lint and CDC checks, synthesis using ASIC or FPGA toolsInterested in using assertions and formal property verification to develop bug free designsExperience of 3+ years in design (uArch, RTL coding, RTL checks and debug)Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.