Senior ASIC Physical Design Engineer

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII except DFT & P&R: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow.Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.What you’ll be doing:Chip integration and netlist generationSynthesis, Netlist quality check, Formal Verification and constraints creation and validation, timing budget.Co-work with PR engineers to implement chip partition and floorplanWork in conjunction with RR engineers to achieve timing closure for both partition and full chip levelAchieve special timing closure, such as io, test, clock etc.Function eco creationDevelop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)Flow automation development, Methodology in any of above areas.What we need to see:BSEE, MSEE is preferredProject experience in IC design implementationCourses taken in circuit design, digital designHand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) is preferredWays to stand out from the crowd:  Proficient user of Perl, Python or TCL is preferred Excellent English communication skillNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you!