Senior Design Verification Engineer

Our team belongs to the MMPLEX Video team, we develop the industry-leading encoder and coder engines supporting multiple video codecs:(h264, HEVC, av1, etc), and the computer vision engines. These engines are wildly used in Tegra and GPU chips and servers for stream gaming, video transcoding, CV, etc.What you’ll be doing:Be responsible for end-to-end verification from IP to Tegra/GPU full-chip for video and computer vision engines.Experience or take the charge  full verification process:Define verification strategy and test plan.Coverage Driven verification flow, formal verification, randomization flow, etc.IP sign-off and interaction with full-chip verification.Besides the traditional ASIC verification, you will also get the opportunity of embracing the High-level synthesis (HLS) verification methodologyWhat we need to see:BS (or equivalent experience) / MS in electrical / computer engineering and related: 3+ years MS or 5+ years BSFamiliar with verification methodology, tools, and flowProgramming skills in System Verilog, Perl, and C/C++Ways to stand out from the crowd:Fully experienced verification flow: know the typical milestones and the related verification action and release. The ability to use proper metrics to present and monitor verification status. Complex TB setup experience and skills : SVA, functional coverage group, random constraint, etc.Background in UVM and System C is a big plusExperience in video codec and image processing projectsExcellent script skills in Perl, Python, or shell