Design Verification Engineer (NCG)

Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity. We are looking for a NCG Verification Engineer to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems.  Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools. Basic qualifications: Pursuing BS or MS in EE/CS or related fields. Minimum GPA: 3.5 Hardware engineering background with an emphasis in VLSI or Computer Architecture. Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture. Authorized to work in the US and start immediately. Required experience : Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog. Familiarity with verification methodologies like UVM, functional coverage, assertions. Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++. Preferred experience: Real-world design and/or verification in Verilog/System Verilog. Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes. Familiarity with Synopsys EDA tools. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.