Senior Firmware Engineer – Compression and Encryption

Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity. Job Description: As an Astera Labs Senior Firmware Engineer, you will develop SW and FW mechanisms to enable offload engines for encryption/compression. Your knowledge and experience in developing firmware solutions for ARM/RISC-V based SoCs will help drive critical feature sets in Astera Labs’ products. Basic qualifications: Bachelors or Masters in Electrical Engineering / Electronics / Computer Science or related fields. Embedded FW development for SOCs that are ARM/RISC-V based. Required experience : 5+ years of experience in software development on offload engines 5+ years of experience dealing with compression and/or encryption algorithms Deep experience in X86 based architectures that deal with DMA engines, tuning of offload engines targeting compression of encryption Fluency with compression algorithms for latency and bandwidth is a must. Experience dealing with optimizing for latency, BW from the host and also to cutting-edge backend memory sub-systems like DDR5/MRDIMMS. Strong Firmware development skills in C within Embedded environments Good understanding of DDR4/5, Optane memory technologies at the controller and PHY Level Good knowledge in DDR training and/or controller features including RAS Ability to plan implementation and unit level testing of DDR features Preferred experience: Post-Silicon validation and bring-up of memory interfaces. Familiarity with RMT/MRC related code for memory optimization Knowledge of memory performance tuning for latency and bandwidth We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.