System Validation Engineer

Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity. Job Description The mission of this role is to perform system validation for Astera Lab’s highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more. Escort our customers when bringing up their systems equipped with our devices, help them maximize performance, understand issues and drive them into full production. You will be part of the new site located at Israel (Haifa – Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your new journey at Astera Labs Israel. Basic qualifications   Strong academic and technical background in electrical or computer engineering ≥5 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence  Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind! Required experience Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, Ethernet. Silicon/System bring-up, validation, and debug experience, including customer’s systems. Familiarity with DDR memory standards with experience in system testing, characterization, margin analysis and optimization Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites. Familiarity with lab testing automation techniques Preferred experience   Ability to interface with memory devices at the ioctl/memio/memap level; familiarity with device trees and related debug techniques. C\C++ for embedded FW and device drivers Familiarity with CXL compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms. Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working on SoC HW/FW to improve memory calibration and tuning sequences. Knowledge of memory subsystem compliance from a data integrity and RAS is a plus. Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc. Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis Astera Labs is a young light-footed company, allowing our engineers to fully exploit their creativity, innovative thinking to enable you to grow up your engineering capabilities to the maximum! We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.