Senior System Validation Engineer

Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity. Job Description The mission of this role is to develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar. Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion, and work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions. Basic qualifications   Strong academic and technical background in electrical or computer At minimum, a Bachelor’s is required, and a Master’s is preferred. ≥5 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence  Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind! Required experience   Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, Ethernet. Silicon/System bring-up, validation, and debug experience, including in customer systems. Familiarity with DDR memory standards with experience in system testing, characterization, margin analysis and optimization. Ability to interface with memory devices at the ioctl/memio/memap level; familiarity with device trees and related debug techniques. A strong background in developing bench automation techniques, especially using Python , with emphasis o . n execution efficiency, repeatability, and reporting. Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites. Preferred experience   Working knowledge of C or C++ for embedded FW and device drivers. Familiarity with CXL compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working on SoC HW/FW to improve memory calibration and tuning sequences. Knowledge of memory subsystem compliance from a data integrity and RAS is a plus. Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc. Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.   We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.