Senior Digital Design Engineer: RISC Based

Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity. Job Description We are looking for Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration for RISC-V based SoCs. The candidate must have demonstrated experience in executing complex processor based designs and deep knowledge of memory and interface protocols such as PCI-Express (Gen-4 and above), DDR, NVMe, etc. Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred. 5 years’ experience supporting or developing complex RISC-V Based SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required experience: Architecture and design of RISC-V CPU core based designs. Design implementation of new features and ISA extensions in RISC-V CPU cores. Proven expertise with coherency protocols targeting cloud-scale BW and latency requirements. Proven expertise in architecture and design of RISC based SOC and trusted security environments. Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production. Experience with Cadence and/or Synopsys digital design tools/flows Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Pre and Post Silicon bring-up and debug expertise. Preferred experience: Knowledge of offload engines like memory compression, encryption and encapsulation Knowledge of boot and BIOS environments for bring up. Knowledge of memory architectures in clustered processor designs. Firmware development with C-language, scripting with Python or other equivalent programming languages. Development/support for PCIe or Ethernet Switch products. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.