The complexity of the chip has greatly increased over the years. We are now packing hundreds of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip Design (SOCD) group is looking for a top ASIC Design Engineer. You should have real passion for RTL design methodologies and implementation that enable high quality system-level IP design and robust QA checks at multiple environment levels (e.g., unit, sub-system, and SOC).What you’ll be doing:Be an integral part of the team defining and developing system-level RTL and methodologies to measure performance on the industry's leading GPUsDesign and implement RTL features (microarchitecture and RTL)Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)Define, develop, and automate flows and methodologies to efficiently build and support a system-level IPCo-work with verification engineers to sign off the designWork with architects, designers, and SW engineers to accomplish your tasksWhat we need to see:MS in Electrical or Computer Engineering with 3 years of relevant industry experienceHave super scale project design experience. Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design/implementation flow, and design automationGood understanding of SOC architecture (e.g., CDC, multiple-power domains, performance analysis, latency, and data flow)Have good understanding/management on task dependency and experienced in working at complex tree.Strong coding skills in Perl or other industry-standard scripting languagesExcellent debugging and analytical skillsExposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Verdi, GDB)Great communication and collaboration skills to interact within the team and with cross functional teamsWays to stand out from the crowd:Performance Monitor background
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