Design Verification Engineer

Summary Posted: Aug 28, 2024 Role Number: 200565429 The people here at Apple don’t just build products — they build the kind of wonder that’s revolutionized entire industries. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do, from amazing technology to industry-leading environmental efforts. Join Apple, and help us leave the world better than we found it. Imagine what you could do here! As a member of design verification team, you will have the responsibility for construction of verification environments, coding of test scenarios and assertions. In this capacity, your role will involve close collaboration with analog and digital design engineers. Description Description Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design Minimum Qualifications Minimum Qualifications Typically requires a minimum of 5 years of experience in System Verilog or other verification language Knowledge of constrained random verification environments. Hands-on experience with Assertion Based Verification Knowledge with Object Oriented Programming Key Qualifications Key Qualifications Preferred Qualifications Preferred Qualifications Knowledge of one of verification language (UVM, OVM, or VMM). Familiarity with system design using C(C++) or Verilog. Basic design background in support of verification results analysis. Education & Experience Education & Experience Additional Requirements Additional Requirements More