Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.
As an Astera Labs’ Semiconductor Packaging Engineer (NCG), you will be part of the packaging team that develops Astera Labs’ portfolio of connectivity products in the world’s leading cloud service providers and server and networking OEMs. You will partner with world-class suppliers to develop IC packaging solutions, resolve multi-disciplinary packaging issues, and participate in cross-functional teams in support of product qualification and production. You will be directly involved with businesses to define, design, develop and qualify IC packages, including for example feasibility study, conducting electrical models, establishing design rules, package co-design, design of experiments, program management and risk management.
Basic qualifications:
B.S. or M.S. in electrical / material / mechanical engineering
Cumulative 3.5/4.0 GPA, or higher
Required experience :
Focused course work and background in communication systems and signal analysis (e.g., RF/Microwave Engineering, Signal and Power Integrity, etc.)
Basic understanding or course work in semiconductor manufacturing
Ability to work and collaborate effectively with people in different functions and multi-disciplinary domains
Ability to manage multiple projects at the same time with dynamic priorities in a fast-paced environment
Strong time management skills and strong written and verbal communication skills
Preferred experience:
Understanding of signal and power integrity, or course work in RF engineering, microwave engineering, or EM theory
Knowledge of semiconductor multi-layer flip-chip package manufacturing flow is a plus (materials, assembly, reliability, manufacturing processes, yield analysis)
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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