We, at NVIDIA, want to find and bring the brightest young technologists of our generation to do their life’s best work at NVIDIA.We are hiring across multiple positions in our HW teams and a brief about the teams and their requirements is given belowGPU ARCHITECTURE TEAMGPU architecture team is engaged in the development of industry leading high performance and power efficient GPUs.Specific areas include architecture modeling, analysis and performance verification. The team works on GPUs across all application domains such as gaming for PC and mobile devices, professional graphics & visualization and high-performance computation.Skills you will use/develop:C++ modeling, test developmentRTL design, debugASIC design & verification tools, methodologiesComputer architecture, Graphics, GPU micro-architecture, parallel computingPerformance evaluation, analysis and debugPerl/Python scriptingAreas you will be working on:COMPUTER ARCHITECTURE; MEMORY SYSTEMS ARCHITECTURE, COMPILER ARCHITECTURE/PERFORMANCE MODELINGGPU ASIC DESIGN / VERIFICATION TEAMToday NVIDIA’s GPUs simulate human intelligence, running deep learning algorithms and acting as the brain of super computers, robots, and self-driving cars that can perceive and understand the world We are seeking a passionate, innovative, and highly motivated senior verification engineers to join us in the development of the next generation of PCI Express controllers used in NVIDIA'sGPUs and SOCs In this position, you will be responsible for verification of the ASIC design, architecture and micro architecture using advanced verification methodologies You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design You will be working with architects, designers, pre and post silicon verification teams to accomplish your tasksWhat you’ll be doingDevelop test plans, tests and verification infrastructure for PCIE at IP/sub system/SOC levelCreate verification environment using UVM methodologyCreate reusable bus functional models, monitors, checkers and scoreboardsDrive functional coverage driven verification closureWork with architects, designers and post silicon teamsWays to stand out from the crowd:Good knowledge of PCIE protocol Gen 3 and aboveGood debugging and problem-solving skillsGood communication skills and ability desire to work as a team playerTEGRA SOC DESIGN & VERIFICATIONTegra ASIC team (Design Verification)As a Hardware Engineer at NVIDIA you will design and implement the industry's leading Graphics, Video and Mobile Communications Processors. Specific areas include 2D and 3D graphics, mpeg, video, audio, network protocols, high-speed IO interfaces and bus protocols, and memory subsystem design. You will be responsible for Architecture and micro-architecture design of the ASICs, RTL design and synthesis, Logic and Timing verification using leading edge CAD tools and Semiconductor process technologiesAreas you will be working on:ASIC, RTL, DESIGN AND VERIFICATION OF PROCESSORSLow Power verificationPower Estimation and ModelingPCIe Design verificationFunctional / Formal verificationCPU VERIFICATION TEAMAs a design verification engineer in the Nvidia's CPU team, you will be working on the next generation of 64bit ARM architecture-based CPUs and SOCs. As part of this assignment, the intern will get a chance to learn about computer architecture at a very granular level, System Verilog, Unit/Cluster /SOC Verification, cutting edge verification methodologies and C/C++/ASM programming. The intern also will get an opportunity to get familiar with industry standard tools in verification and validation. During the course of the internship, the intern will contribute to building test benches, developing architectural simulators, modifying random instruction generators and creating stimulus for verifi ation and validation of different units of the CPU and SOC.Areas you will be working on:Computer ArchitectureDigital Design and Programming in C/C++/PerlARM, CPU Design and Verification/ ValidationASIC-PD (Timing Closure / VLSI)VLSI team works in the areas of RTL Design, Verification, Design for Test, CAD tools, Synthesis, Timing, Place & Route, Circuit Design, Silicon Bring-up and Characterization. Responsible for state-of-the-art methodologies, tools, flows and project execution on all Nvidia GPU, CPU, Auto, and Switch chips. As a team member you will be working on one or more such areas.Skills you will use/develop:RTL Design, VCS, SV, UVM, FormalVerilog, C/C++, Python, TCL, PerlLogic Scan Test, Memory Test, High-speed IO Test, In-System TestSynthesis, Timing Closure (Primetime)Physical Design, Innovus, ICC2, Physical extraction, Place and Route, FloorplanSRAM, Analog, Digital circuit design, Hspice, EMIR, Silicon Correlation (ATPG, data visualization & analysis)Layout (Cadence Virtuoso)Silicon characterization for ageing, DPPM, Signal Integrity, Power Integrity, and familiarity with PC/SOC sub-system ArchitectureINFRASTRUCTURE TOOLS DEVELOPMENT (Trace Tools / Graphics)A key part of NVIDIA’s strength is our unique tools for analysis, visualization, debug and automated regressions. We are looking for bright engineers to paticipate in our fast-paced Agile software team and to continue and improve our extremely high production quality standards. These tools are used by all the engineers in NVIDIA. We are continuously pushing the envelope and needing the next generation of tools to enable the next generation of chips. The tools we build involve high compute infrastructure to allow very large scale distributed, cross-platform runs of mission critical proprietary applications, creating integrated development and debugging environments (such as Eclipse), implementing software engineering methodologies and tools to improve code qua ity, creating and driving quality build and release processes, and driving the peformance improvement of chips we developAreas you will be working onObject-oriented programming and design background: Object Oriented Perl, C++ or JavapreferredInterpreted language skills – Object Oriented Perl preferredExperience in software development life cycle in Linux based platforms preferred
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