Design Implementation Engineer

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Candidate would be required to work on modeling and Design Implementation activities related to complex digital and mixed signal IP blocks used in the development of Broadcom’s ASIC / SoC products.  Activities include development, verification, and deployment of models for emulation and simulation, design-for-test (DFT), and timing analysis. Required to maintain integration guides and release notes used with the deployment of IP.  Assemble, audit, and release packages consisting of logical and physical views to support ASIC developments.  Additionally, the candidate would be required to do block-level synthesis, verification (functional, static, formal), and timing analysis.  Candidate will work closely with the IP design teams to accomplish the modeling and design implementation activities. The engineer will work with the internal ASIC / SoC teams and Broadcom customers to support integration, simulation, DFT, synthesis, timing analysis and closure, and physical implementation involving the IP blocks. Contribute to maintaining IP integration and user guides for supporting chip-level functions such as IP integration, RTL and gate-level verification, synthesis, design-for-test (DFT), synthesis, physical layout, timing analysis, and manufacturing testing. Assist in analyzing and debugging customer problems involving the use of the IP models. Will be exposed to various IP and ASIC / SoC developments. Opportunities for customer interaction and other high profile activities are available to members of this team.In this role, the candidate will apply Broadcom's proven modeling and design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.Requirements:Candidate should have experience with functional verification, synthesis and/or timing (constraints, STA), static and formal verification. Experience with functional verification using Verilog/SystemVerilog including advanced verification concepts and methodologies (e.g., UVM). Experience with constraints development, constraints validation, and timing analysis. Experience with tools such as VCS/Xcelium, Zebu/Palladium/Veloce, Design Compiler, PrimeTime, Formality/LEC. Experience with Perl/Python and Tcl. Good problem solver and must have an appreciation for version control and developing, maintaining, and using automated processes where applicable. Capable of working independently and experienced in working in a global team and dynamic environment.Should possess ability to learn and adapt to new tools and methodologies on the fly.  Possess excellent communication skills.Hands on experience with timing analysis and place and route tools for block level / ASIC / SoC is a plus.Education and Experience required:BS in Electrical Engineering / Computer Engineering or related fieldAdditional Job Description:Compensation and BenefitsThe annual base salary range for this position is $51,000 - $85,000This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.