Experienced AMS Physical Design Engineer (M, F, D)

Summary Posted: Jan 31, 2024 Role Number: 200536941 At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a ground-breaking and uncommonly dedicated Physical Design Engineer in Munich. As a member of our multifaceted group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. In this role, you will be at the center of a PHY design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class PHY designs. You will be required to do physical designs of best in class PHY design. Key Qualifications Key Qualifications - The ideal candidate will have experience on high PHY and/or SOC designs: - Deep Knowledge about industry standards & practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route. - Experience in developing and implementing Power-grid and Clock specifications - Deep Understanding of all aspects of Physical construction, Integration and Physical Verification - Proven Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes - Power user of industry standard Physical Design & Synthesis tools - Deep Understanding of scripting languages such as Perl/Tcl - Solid understanding of Extraction and STA methodology and tools - Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level - Ability to fluently speak and write in English Description Description Responsibilities include especially, but are not limited to: - Generate block/chip level static timing constraints. - Create full chip floor-plan including pin placement, partitions and power grid. - Develop and validate dedication low power clock network guidelines. - Perform block level place and route and close the design to meet timing, area and power constraints. - Generate and Implement ECOs to fix timing, noise and EM IR violations - Run physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. - Participate in establishing CAD and physical design methodologies for correct by construction designs - Assist in flow development for chip integration As a Physical Design engineer you will contribute to all phases of physical design of dedication PHY design from RTL to delivery of our final GDSII. Education & Experience Education & Experience Additional Requirements Additional Requirements