Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:The successful candidate will be responsible of:DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BISTAnalysis to improve the testability of Digital design at Block and chip level.Implementation of DFT logics for Digital and Mixed Signal IP. Perform ATPG pattern generation / Verification including SSA /Transition/ Path Delay and IDDQ pattern. Deliver high quality ATE patterns for production ATE testingProvide test pattern support to ATE engineering team for First Proto bring up and failure analysis in the use of ATPG test and scan/debug featuresExperienceBachelor degree or equivalent in Electrical or Computer EngineeringFamiliar with HDL design languageGood working knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell, Perl)Knowledge of ASIC design is a must, and ATE test is a plusStrong problem solving skillsTeam player with strong communication skillsBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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